Design Enhancement of Combinational Neural Networks Using Hdl Based Fpga Framework for Pattern Recognition

The fast emerging highly-integrated multimedia devices require complex video/image processing tasks leading to a very challenging design process; as it demands more efficient and high processing systems. Neural networks are used in many of these imaging applications to represent the complex input-output relationships. Software implementation of these networks attain accuracy with tradeoffs between processing performance (to achieve specified frame rates, working on large image data sets), power and cost constraints. The current trends involve conventional processor being replaced by the Field programmable gate array (FPGA) systems due to their high performance when processing huge amount of data. The goal is to design the Combinational Neural Networks (CNN) for pattern recognition using an FPGA based platform for accelerated performance. The enhancement in speed and computation from the hardware is being compared to the software (using MATLAB) model. The employment of HDL on the FPGA enables operations to be performed in parallel. Thus allowing the exploitation of the vast parallelism found in many real-world applications such as in robotics, controller free gaming and sign/gesture recognition. As a validation of the CNN hardware model a case study in pattern recognition is being explored and implemented on Xilinx Spartan 3E FPGA board. To measure the quality of learning in the trained network mean squared error is used. The processing performance of this non-linear stochastic tool is determined by comparing the HDL (parallel model) simulations with the MATLAB design (sequential model). The gain in training time and memory used for processing is also derived.